Senior Verification Engineer - Networking

Senior Verification Engineer – High-Speed Networking (Contract)

We are recruiting for a Senior Verification Engineer to work on advanced high-speed networking and SoC IP programmes. This is a hands-on contract role focused on pre-silicon verification using modern methodologies and protocols.

You will be responsible for verifying complex IP and SoC designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments.

Key Responsibilities

• Design and implement UVM / SystemVerilog verification environments
  
  
• Deliver constrained-random verification and achieve coverage sign-off
  
  
• Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5)
  
  
• Integrate and use Verification IP (VIP)
  
  
• Develop and maintain Python-based regression and CI workflows
  
  
• Collaborate with design, architecture, and SoC teams
  
  Essential Skills & Experience
  
  
• Strong experience as a Verification Engineer / Design Verification Engineer
  
  
• Expert knowledge of UVM and SystemVerilog
  
  
• Experience with Ethernet, PCIe, AMBA / AXI
  
  
• Proven ownership of test plans and coverage closure
  
  
• Python scripting and Git-based workflows
  
  
• Experience in ASIC, SoC, or IP verification environments
  
  Desirable
  
  
• Experience with Vivado / Vitis or adaptive SoC flows
  
  
• Embedded processor co-simulation or SoC debug exposure
  
  This role suits a senior, hands-on verification specialist who enjoys working on complex, high-performance hardware designs.
  
  Apply now to discuss details confidentially